@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO225 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":158:0:158:5|There are no possible illegal states for state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog)); safe FSM implementation is not required.
